16F88 B. Dring bdring@eng-serve.com 0.1 2007:08:07 (2007) B. Dring Prelimianry version...use with caution External Internal RC 31.25 kHZ Internal RC 125 kHZ Internal RC 250 kHZ Internal RC 500 kHZ Internal RC 1 MHZ Internal RC 2 MHZ Internal RC 4 MHZ Internal RC 8 MHZ PORTA PORTB Select A/D Channel (checked=AD) AN0-AN6 Fosc/2 Fosc/8 Fosc/32 FRC (clock derived from the internal A/D RC oscillator) Fosc/4 Fosc/16 Fosc/64 FRC (clock derived from the internal A/D RC oscillator) Right justified. Six (6) Most Significant bits of ADRESH are read as 0 Left justified. Six (6) Least Significant bits of ADRESL are read as 0 Enable ADC TMR0IF: Timer 0 Overflow INT0IF: External interrupt RBIF: PORTB Change Interrupt EEIF: EEPROM Write Operation Interrupt OSFIF Oscillator Fail Interrupt ADIF: A/D Converter Interrupt RCIF: USART Receive Interrupt TXIF: USART Transmit Interrupt SSPIF: Synchronous Serial Port (SSP) Interrupt CCP1IF: CCP1 Interrupt TMR2IF: TMR2 to PR2 Match Interrupt TMR1IF: TMR1 Overflow Interrupt CMIF: Comparator Interrupt Capture/Compare/PWM disabled Capture mode, every falling edge Capture mode, every rising edge Capture mode, every 4th rising edge Capture mode, every 16th rising edge Compare mode, set output on match (CCP1IF bit is set) Compare mode, clear output on match (CCP1IF bit is set) Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) PWM mode CVREF voltage level is output on the RA2/AN2/CVREF/VREF- pin 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size 0.25 CVRSRC to 0.72 CVRSRC with CVRSRC/32 step size